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Physical Design Engineer

  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Deliver physical design of end-to-end IPs and SoCs.

 

What are the top non-negotiable skill sets required to be succesful in this role?

  • Experie3nce in sub-10nm ASIC synthesis, Design for Test (DFT), floorplan, place and route (PnR or P&R), static timing analysis (STA), and power analysi/s.
Key Requirements:
  1. Synthesis and timing closures for ASIC deliverables in sub-15 nm geometries with very low power targets.  Tools such as Synopsys Design Compiler (DC).  FPGA synthesis and timing tools are a plus here, as well, but not a substitute for ASIC flow.
  2. Scripting language experience including Python and TCL.  Other languages are a plus.
  3. XFN Collaboration with all teams to complete ASIC deliverable flows e.g. design, verification, power, performance, physical design, program management, etc.

Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience 

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