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Design Verification Engineer

RESPONSIBILITIES

·         Write and augment existing testplans.

·         Implement testbench and scoreboards / checkers.

·         Implement test sequences as per plan and debug failures

·         Achieve 100% functional and code coverage

·         Work closely with designers, micro architects & f/w to resolve issues

·         Ability to communicate & articulate clearly progress / issues with project leads

MINIMUM QUALIFICATIONS

  • 5+ years of proven experience as a DV engineer
  • Hands on experience with SV and UVM
  • Hands on Experience with executable test plans and Coverage Driven verification
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • Familiarity with C/C++

 

PREFFERED QUALIFICATIONS

  • Python (or similar) scripting language
  • ASIC design experience
  • Experience in DSP based Audio or Computer Graphics or Compression' is desirable

 

Bachelor's degree

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