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ASIC Design Verification Engineer

Create test plan for assigned ASIC blocks or features.

Create self checking test bench and test cases using SystemVerilog and UVM methodology.

Define functional coverage metrics to measure and report progress.

Run random test regression to maximize design coverage.

Debug failing test cases using Verdi or other waveform debugging tool.

Collect and analyze code and functional coverage reports to improve test bench and test cases to reach 100% goal.

Experienced in creating test plan for ASIC blocks or features.

Experienced in self checking test bench and test cases using SystemVerilog and UVM methodology.

Experienced in defining functional coverage metrics.

Experienced in Cadence or Synopsys HDL simulator.

Experienced in Verdi or other waveform debugging tool.

Experienced in analyzing code and functional coverage reports.

Bachelor degree in Electrical Engineering, Computer Engineering, or Computer Science.

 
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