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Verification Engineer

5+ years of proven experience as a Digital Design and verification 
Hands on experience with SV and UVM
Hands on Experience with executable test plans and Coverage Driven verification
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Familiarity with C/C++
 
Write and augment existing test plans.
 Implement testbench and scoreboards / checkers.
 Implement test sequences as per plan and debug failures
 Achieve 100% functional and code coverage
Work closely with designers, micro architects & f/w to resolve issues
 Ability to communicate & articulate clearly progress / issues with project leads
ARTICULATE 
DIGITAL DESIGN 
ALGORITHMS 
SYNOPSYS 
TEST PLANS  
 
Additional Skills: 
C++ 
CADENCE 
COMPUTER VISION 
DEBUG 
DECISION SUPPORT PANEL 
DSP 
ENGINEER 
IPS 
PYTHON 
SCRIPTING 
SIMULATIONS  
 

Bachelors Degree in Electronics or comnputer Science with logic design exposure . 

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