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Design Verification Engineer

  • Write and augment existing testplans.
  • Implement testbench and scoreboards / checkers.
  • Implement test sequences as per plan and debug failures
  • Achieve 100% functional and code coverage
  • Work closely with designers, micro architects & f/w to resolve issues
  • Ability to communicate & articulate clearly progress / issues with project leads

 

LOCATION OF ROLE CAN BE EITHER MPK (FB HQ) OR REDMOND, WA

PLEASE OPEN SOURCING PIPLINES TO BOTH LOCATIONS AND INFORM CANDIDATES THEY CAN WORK AT EITHER CAMPUS

 

 

Must Have:

  • 7+ years of proven experience as a DV engineer
    • Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
  • Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology) 
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • 2+ Years of experience with C/C++

Wish List/ Nice to Have:

  • Python (or similar) scripting language
  • ASIC design experience
  • Experience in Computer Graphics or Compression is desirable
  • MSEE/CS or equivalent experience

 

Interview: 

 

Coding Screen: 30 min SV & C++

Onsite Interview: 60 min w/ Team

  • Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
  • Master's Degree preferred but not required
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