View Our Website View All Jobs

ASIC Implementation Engineer

  • Execute ASIC Integration tasks, preparing full-chip RTL for Synthesis. 
  • Developing scripts for Logic and Physical Synthesis, Timing Constraints development, Run Logic/Physical Synthesis and generate Optimized Gate Level Netlist for Timing, Area, Power 
  • Perform Power Estimation at RTL and Gate Level Run Formal Verification checks between RTL and Gate level netlist and debug the Logic Equivalency failures 
  • Perform RTL Lint checks and work with the Designers to create Lint Waivers Perform Clock Domain Crossing, Reset Domain Checks 
  • Work closely with the Design Engineers in supporting them with the handoff tasks. Interact with physical design engineers and providing them with floor plan feedback.
  • Good Experience in Design Integration and Front End Implementation 
  • Strong Synthesis Background, Timing Constraints Development, Floorplanning and STA Experience Knowledge of RTL coding using Verilog/System Verilog 
  • Good Understanding of Timing/physical libraries, SRAM Memories 
  • Experience with PPA Analysis and techniques for reducing power 
  • Experience with Clock Domain Crossing, Reset Domain Crossing, LEC 
  • Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl, TCL, and Make 
  • Excellent communication skills.

Bachelors or Masters in Electrical Engineering

Read More

Apply for this position

Required*
Apply with Indeed
We've received your resume. Click here to update it.
Attach resume as .pdf, .doc, .docx, .odt, .txt, or .rtf (limit 5MB) or Paste resume

Paste your resume here or Attach resume file

150