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Hardware Engineer IV

  • Integrate compression codec IP blocks into subsystems for emulation systems
  • RTL and Verification of custom image processing blocks
  • Setup simulation environment and run simulations to verify design​

 

Minimum Qualifications:

  • 4+ years’ experience with Verilog RTL design and verification.
  • 2+ years’ experience FPGA-based design
  • Experience with scripting languages (shell script, python)
  • BSEE/CS or equivalent experience

Preferred Qualifications:

  • Ability to collaborate and communicate effectively in a team environment
  • MSEE/CS or equivalent experience
  • Experience with Video Compression algorithms

• Bachelor degree in Electrical/Computer Engineering or Computer Science

Master's Degree preferred

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